Test Vector Reordering Method for Low Power Testing

The book "Test Vector Reordering Method for Low Power Testing" offers a comprehensive examination of algorithms for reordering test vectors to minimize power consumption during the testing phase of VLSI circuits. In today's design and testing practices, reducing power consumption during testing is crucial, as the test vectors generated by automatic test pattern generators are statistically independent, leading to increased power consumption. The book describes the development of a reordering algorithm based on graph theory and heuristic concepts to find suboptimal solutions. Five functional metrics are considered to effectively reorder the test vectors. Additionally, a method for replacing "Don't Care" states is introduced to further reduce transitions in the test set. The implementation and simulation of these methods on ISCAS85 benchmark circuits demonstrate significant improvements in terms of transitions and average power consumption.