Name: SystemVerilog for Verification
Price: 115 CHF
Availability: InStock
ISBN: 9781461407140

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Zurich

Lausanne

Wohlen

Basel

Kriens

Winterthur

Bern

Dietikon

St. Gallen

Geneva

Springer

The textbook "SystemVerilog for Verification: A Guide to Learning the Testbench Language Features" in its third edition offers a comprehensive introduction to the verification features of the SystemVerilog language. Authors Chris Spear and Greg Tumbush convey the concepts and fundamental principles through numerous examples suitable for both experienced verification engineers and students. The new edition includes updated sections on static variables, print specifiers, and DPI according to the IEEE language standard from 2009. Additionally, UVM features such as factories, the test register, and the configuration database are described. At the end of each chapter, exercises are provided to deepen the learners' understanding. The numerous tested code examples on popular SystemVerilog simulators make this book a valuable learning tool for students and professionals in the fields of engineering and IT.

Actual product image SystemVerilog for Verification (English, Hardcover, Chris Spear, Greg Tumbush)

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