Design-for-Test and Test Optimization Techniques for TSV-based 3D Stacked ICs

The book "Design-for-Test and Test Optimization Techniques for TSV-based 3D Stacked ICs" offers a comprehensive analysis of innovative techniques to address the testing requirements of 3D stacked integrated circuits (ICs) that utilize through-silicon vias (TSVs) as vertical connections. The authors, Krishnendu Chakrabarty and Brandon Noia, highlight the key challenges associated with testing 3D ICs and present findings from advanced research in this field. Topics range from die-level wrappers and built-in self-test circuits to test architecture design, test planning, and optimization. This technical book is aimed at professionals and researchers who need an in-depth understanding of the test technology solutions necessary to make 3D ICs both feasible and commercially viable.