Modifiziertes SDM-basiertes Netzwerk auf dem Chip

Moore's Law has driven the scaling of dimensions and performance of digital electronic devices over the past 50 years. As a result, the logic components in a System-On-Chip (SoC) have experienced a dramatic increase in performance. On the other hand, the on-chip connections, which were only considered parasitic loads before the 1990s, have become a real performance bottleneck due to their extremely reduced cross-sectional dimensions. The continuously decreasing cross-sectional dimensions of the interconnections lead to an increase in resistance. All of this combined results in a deterioration of the RC time constant of the metal wires on the chip. Consequently, the ongoing performance degradation of on-chip Cu/Low-k connections is one of the biggest challenges in maintaining Moore's Law, while the scaling of transistor dimensions has led to an unstoppable improvement in delay.