Name: Core i5-9500 processor 3 GHz
Brand: Intel
SKU: 37700898
Price: 198.58 CHF
Availability: InStock

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Intel

Experience exceptional performance for home and business PCs with multiple cores for gaming, creativity, and multitasking.

Actual product image Intel Core i5-9500 processor 3 GHz (LGA 1151, 3 GHz)

Key specifications

Processor family

Number of threads

NPU power

Max. TDP

The thermal design power (TDP), sometimes called thermal design point, refers to the maximum amount of power the cooling system in a computer is required to dissipate. For example, a laptop's CPU cooling system may be designed for a 20 watt TDP, which means that it can dissipate up to 20 watts of heat without exceeding the maximum junction temperature for the computer chip. It can do this using an active cooling method such as a fan or any of the three passive cooling methods, convection, thermal radiation or conduction. Typically, a combination of methods is used. The TDP is typically not the most power the chip could ever draw, such as by a power virus, but rather the maximum power that it would draw when running "real applications". This ensures the computer will be able to handle essentially all applications without exceeding its thermal envelope, or requiring a cooling system for the maximum theoretical power (which would cost more but in favor of extra headroom for processing power).

L3 Cache

Another issue is the fundamental tradeoff between cache latency and hit rate. Larger caches have better hit rates but longer latency. To address this tradeoff, many computers use multiple levels of cache, with small fast caches backed up by larger slower caches.

Multi-level caches generally operate by checking the smallest Level 1 (L1) cache first; if it hits, the processor proceeds at high speed. If the smaller cache misses, the next larger cache (L2) is checked, and so on, before external memory is checked.

As the latency difference between main memory and the fastest cache has become larger, some processors have begun to utilize as many as three levels of on-chip cache.

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